Flip-flop Characteristic
Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition.
The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications.
Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns.
Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop.
Setup time is the minimum time for the data to be present before the clock.
Hold time is the minimum time for the data to remain after the clock.
