Parallel-to-Serial Conversion

In order to construct a right shift register, the outputs of each flop-flop (Q and ) must be connected to the inputs (J and K or D) of the flip-flop to its right.
A shift register must also have all clock inputs ties to a common clock signal so they will all change state at the same time.
The asynchronous inputs (set and reset) for each flip-flop can be used to provide the parallel load.
The output of a right shift register will appear at the Q output of the LSB. The LSB will appear first at the output.
The output of a left shift register will appear at the Q output of the MSB. The MSB will appear first at the output.